Fault tolerance estimation in digital circuits with visualised generative networks

arXiv:2605.15212v2 Announce Type: replace-cross Abstract: We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, inc

Source: arXiv cs.AI — read the full report at the original publisher.

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