Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation

arXiv:2605.26498v1 Announce Type: new Abstract: Large language models (LLMs) have improved Verilog generation from natural-language specifications, but most pipelines still treat generation as isolated sampling followed by functional checking. This is insufficient for practical RTL design, where useful Verilog must be correct, synthesizable, timing-conscious, and friendly to downstream hardware objectives. We present Verilog-Evolve, a feedback-driven framework for versioned Verilog refinement and cross-session skill evolution. For each task, Verilog-Evolve generates diverse minor candidates, e

Source: arXiv cs.CL — read the full report at the original publisher.

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