Imec’s Zsolt Tokei and Arm’s Mohamed Awad explain why CMOS 2.0 could redefine semiconductor scaling beyond chiplets. The post Beyond Chiplets, CMOS 2.0 Moves Scaling into the Circuit appeared first on EE Times .
The semiconductor industry is continuously pushing the boundaries of scaling, and traditional chiplet approaches are beginning to face physical limits, driving innovation towards new paradigms like CMOS 2.0.
CMOS 2.0 represents a significant evolution in semiconductor manufacturing, potentially redefining how computational power is scaled and integrated, impacting all sectors reliant on advanced silicon.
The focus of semiconductor scaling shifts from primarily die-level integration (chiplets) to more circuit-level and intra-wafer advancements, offering new avenues for performance and efficiency gains.
- · ASML
- · Imec
- · Taiwan Semiconductor Manufacturing Company (TSMC)
- · Applied Materials
- · Companies heavily invested only in legacy packaging
- · Firms unable to adapt to new fabrication complexities
Next-generation chips will achieve higher transistor densities and improved power efficiency through advanced circuit-level integration.
This deepens the competitive moat for leading-edge foundry services and equipment providers capable of implementing these complex manufacturing processes.
The increased sophistication of chip design and manufacturing could exacerbate global supply chain dependencies and raise entry barriers for new semiconductor players.
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Read at EE Times