BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models
arXiv:2606.13747v1 Announce Type: cross Abstract: Accurate power estimation is important for understanding and optimizing CPU power behavior, yet practical workflows often rely on simulation-derived information or post-silicon analysis. In this work, we present BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design. BigPower leverages large language model-based representations together with architectural hierarchy, module connectivity, configuration parameters, and workload context to estimate module-level power consumption direct
The increasing complexity and power demands of modern CPUs and AI models necessitate more advanced and efficient power estimation techniques during the design phase.
Accurate, early-stage power estimation is crucial for optimizing CPU design, reducing development costs, and improving the energy efficiency of compute infrastructure.
This development allows for more granular and hierarchical power estimation using AI, shifting traditional reliance on post-silicon analysis or less sophisticated simulation models.
- · Semiconductor design companies
- · Hyperscale data centers
- · AI hardware developers
- · EDA tool vendors
- · Less efficient CPU architectures
- · Traditional, manual power estimation methods
BigPower enables more optimized and energy-efficient CPU designs by providing fine-grained power estimation early in the design cycle.
Improved CPU energy efficiency could lead to lower operational costs for data centers and reduced environmental impact of compute infrastructure.
This could accelerate the development of more powerful and complex AI systems by enabling better power management at the architectural level, potentially influencing the 'energy-bottleneck' narrative.
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Read at arXiv cs.LG