Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
arXiv:2602.23334v2 Announce Type: replace-cross Abstract: Neural network accelerators have been widely applied to edge devices for complex tasks like object tracking, image recognition, etc. Previous works have explored the quantization technologies in related lightweight accelerator designs to reduce hardware resource consumption. However, low precision leads to high accuracy loss in inference. Therefore, mixed-precision quantization becomes an alternative solution by applying different precision in different layers to trade off resource consumption and accuracy. Because regular designs for m
The increasing demand for efficient AI at the edge necessitates advanced hardware solutions that balance performance and resource constraints, pushing innovations in quantization and reconfigurable architectures.
This development can significantly improve the efficiency and accuracy of AI models deployed on edge devices, broadening their applicability in critical real-world scenarios.
Hardware accelerators will be capable of more flexibly managing precision in AI computations, leading to better performance for given power and area budgets.
- · Edge AI device manufacturers
- · Semiconductor companies
- · AI developers
- · IoT industry
- · Companies relying on energy-inefficient AI hardware
- · Developers restricted by fixed-precision quantization
Improved performance and broader deployment of AI applications on resource-constrained edge devices.
Reduced energy consumption for a given level of AI inference capability, impacting sustainable computing and operating costs.
New classes of always-on, intelligent edge devices and applications become viable, extending AI's reach into more personal and pervasive contexts.
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Read at arXiv cs.AI