arXiv:2602.19330v2 Announce Type: replace Abstract: Graph Neural Networks (GNNs) are increasingly explored for physical design analysis in Electronic Design Automation, particularly for modeling Clock Tree Synthesis behavior such as clock skew and buffering complexity. However, practical deployment remains limited due to the prohibitive memory and runtime cost of operating on raw gate-level netlists. Graph coarsening is commonly used to improve scalability, yet its impact on CTS-critical learning objectives is not well characterized. This paper introduces CTS-Bench, a benchmark suite for syste
The increasing computational demands of advanced chip design necessitates innovative approaches to optimize GNN performance, making benchmarks like CTS-Bench critical for accelerating research and adoption.
This benchmark addresses a key bottleneck in applying GNNs to chip design, specifically Clock Tree Synthesis, which is vital for efficient and high-performance semiconductors.
By standardizing the evaluation of graph coarsening techniques for GNNs in Electronic Design Automation, CTS-Bench will accelerate the development and deployment of scalable AI solutions for chip design.
- · Electronic Design Automation (EDA) companies
- · Semiconductor industry
- · AI researchers in GNNs
- · Cloud computing providers
- · Legacy ASIC design methodologies dependent on manual optimization
More efficient and faster design cycles for complex integrated circuits due to improved GNN applications.
Reduced power consumption and increased performance of new semiconductor products.
Enhanced competition in the semiconductor industry leading to further innovation in AI-driven design tools and methodologies.
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Read at arXiv cs.LG