arXiv:2606.23870v1 Announce Type: cross Abstract: PLCverif is the most mature open-source platform for PLC formal verification, developed at CERN and in production use since 2019. Yet it has two fundamental limitations: no support for Ladder Diagram (LD) programs, the dominant PLC notation, and reliance on CBMC as its primary backend, which restricts verification to bounded proofs. The PLCverif authors themselves identified ESBMC as the appropriate backend improvement. Prior work established ESBMC-PLC (a textual LD frontend with k-induction) and ESBMC-GraphPLC (graphical PLCopen XML support);
The continuous evolution of industrial automation and the increasing complexity of PLC programs necessitate more robust verification methods, leading to the development of enhanced open-source tools.
Improved formal verification of PLC programs, especially for dominant notations like Ladder Diagram, enhances industrial control system reliability and cybersecurity, which is critical for infrastructure.
The introduction of ESBMC-PLC+ provides a unified, more capable formal verification framework for PLCs, moving beyond the limitations of previous tools by supporting Ladder Diagram and unbounded proofs.
- · Industrial automation sector
- · Critical infrastructure operators
- · Cybersecurity researchers
- · CERN
- · Manufacturers of unreliable PLC systems
- · Organizations with inadequate testing methodologies
Increased reliability and security of industrial control systems using IEC 61131-3 compliant PLCs.
Reduced operational downtime and fewer catastrophic failures in automated industrial processes due to verified software.
Potential for broader adoption of formal methods in industrial software development, raising standards across the sector.
This signal links to a primary source. Continuum Brief monitors and indexes it as part of the live intelligence stream — we do not republish source content.
Read at arXiv cs.CL