arXiv:2605.15212v2 Announce Type: replace-cross Abstract: We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, inc
The increasing complexity and density of digital circuits, especially for AI applications, necessitate more robust fault tolerance estimation methods to ensure reliability and performance.
Reliable fault tolerance is critical for high-performance computing, AI hardware, and mission-critical systems, directly impacting computational integrity and operational uptime.
This new numerical method offers a more precise way to estimate and potentially mitigate fault tolerance issues in digital circuits, moving beyond traditional simulation limits.
- · Semiconductor manufacturers
- · AI hardware developers
- · High-performance computing sector
- · Design automation tool providers
- · Traditional fault simulation methods
- · Systems with high failure rates due to unestimated faults
Improved reliability and performance of advanced digital circuits, particularly those used in AI and critical infrastructure.
Reduced design iteration cycles and manufacturing costs for complex chips due to more accurate early-stage fault prediction.
Accelerated development of more resilient and energy-efficient AI accelerators and specialized computing hardware.
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Read at arXiv cs.AI