FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
arXiv:2605.20287v1 Announce Type: new Abstract: Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulation sweeps, and many fast predictors ignore layout geometry, missing coupling and layout-dependent effects. The challenge is to jointly represent layout geometry and netlist topology so models capture fine-grained spatial details together with structural connectivity for accurate performance prediction. We introduce FusionCell, a dual-modality predictor that treats rout
The increasing complexity of chip designs and the demand for higher performance necessitate more efficient and accurate prediction methods for standard-cell behavior at an earlier stage of design.
Accurate and fast performance prediction for standard cells can significantly reduce chip design cycles and improve overall chip performance, directly impacting the compute supply chain.
The ability to integrate layout geometry and netlist topology in performance prediction models moves away from slower simulation sweeps and enhances the precision of early design-phase analysis.
- · Semiconductor design companies
- · EDA tool vendors
- · AI hardware developers
- · Traditional simulation-heavy design methodologies
- · Less efficient chip manufacturing processes
Faster and more optimized chip designs become possible due to improved performance prediction.
Reduced time-to-market for advanced chips could accelerate innovation in AI and other compute-intensive fields.
Increased global competition in semiconductor design, potentially leading to more distributed or resilient supply chains.
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