Graph-ESBMC-PLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
arXiv:2606.18941v1 Announce Type: cross Abstract: PLCopen XML defines two encoding formats for IEC 61131-3 Ladder Diagram programs: a textual encoding using elements, and a graphical encoding that represents rung logic as a directed graph of localId/refLocalId connections. ESBMC-PLC supported the textual format but parsed graphical exports from CONTROLLINO, Beremiz, and OpenPLC Editor into an empty GOTO intermediate representation, causing vacuous verification success. This paper presents Graph-ESBMC-PLC, which closes this gap with a DFS-based graphical LD resolver. The resolver traverses the
The increasing complexity and criticality of industrial control systems necessitate robust verification tools, specifically for widely adopted standards like PLCopen XML, where current methods fall short for graphical programs.
Formal verification of PLC programs reduces critical vulnerabilities in industrial automation, impacting infrastructure reliability and cyber-physical security, which is paramount in an increasingly interconnected world.
Previously unverifiable graphical PLCopen XML Ladder Diagram programs can now be formally verified, closing a significant security and reliability gap in industrial control systems.
- · Industrial Automation Sector
- · Cybersecurity Vendors
- · Critical Infrastructure Operators
- · ESBMC-PLC maintainers
- · Malicious Actors targeting industrial systems
- · Companies with poor verification practices
Improved reliability and security of industrial control systems utilizing PLCopen XML graphical programs.
Reduced operational downtime and financial losses due to fewer bugs and vulnerabilities in critical infrastructure.
Accelerated adoption of formal verification techniques across broader industrial software development, potentially influencing regulatory standards for cyber-physical systems.
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