Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
arXiv:2209.00188v4 Announce Type: replace-cross Abstract: Long-latency load requests continue to limit the performance of high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on two key techniques: sophisticated data prefetchers and large on-chip caches. In this work, we show that: 1) even a sophisticated state-of-the-art prefetcher can only predict half of the off-chip load requests on average across a wide range of workloads, and 2) due to the increasing size and complexity of on-chip caches, a large fraction of the latency of an off
This research provides a new approach to a long-standing processor performance bottleneck, leveraging AI techniques that have recently matured.
Accelerating long-latency load requests is critical for improving the performance and efficiency of high-performance processors, directly impacting the capabilities of AI and other data-intensive applications.
The proposed 'Hermes' system introduces perceptron-based off-chip load prediction, potentially offering a more effective solution than current prefetcher and cache designs, which could lead to significant performance gains in future processor architectures.
- · AI hardware developers
- · Hyperscale cloud providers
- · High-performance computing (HPC) sector
- · Semiconductor companies
- · Traditional prefetcher design methodologies
Processor performance for data-intensive workloads improves noticeably.
Reduced need for ultra-large on-chip caches, potentially lowering chip manufacturing costs or increasing available die space for other components.
Enhanced overall AI compute capability without proportional increases in power consumption, further accelerating AI development and deployment.
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Read at arXiv cs.LG