HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
arXiv:2606.13706v1 Announce Type: cross Abstract: We present HierSVA, an integrated suite that combines a pipeline, dataset, and benchmark for LLM-driven hierarchical hardware formal verification. HierSVA-SP pairs an RTL preprocessing toolchain with an LLM-in-the-loop formal verification flow to produce reference SystemVerilog Assertions (SVA) on hierarchical RTL. Applying it to BaseJump STL yields HierSVA-DS, a dataset of 342 modules, with hierarchy metadata and depths 0--9, accompanied by a deep subset of 28 module-bug pairs with natural-language specifications and bug variants. HierSVA-B de
The increasing complexity of hardware design necessitates more automated and robust verification methods, while large language models are reaching capabilities suitable for such specialized tasks.
This development could significantly accelerate the pace and reliability of hardware design, enabling faster innovation in compute and specialized AI chips.
The formal verification of hardware, currently a bottleneck, could become substantially more efficient and less error-prone through LLM-driven automation.
- · Hardware design companies
- · Semiconductor industry
- · AI compute developers
- · EDA tool vendors
- · Traditional hardware verification firms
- · Manual verification engineers
Reduced hardware design cycles and improved reliability of complex semiconductors.
Faster development and deployment of advanced AI accelerators and specialized computing units.
Enhanced self-correction capabilities within hardware design, potentially leading to more resilient and efficient systems.
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Read at arXiv cs.AI