Imec's 2026 roadmap details 0.3nm nodes by 2038, CFET transistors become viable at 0.7nm — company redefines Moore's Law as cell sizes gain importance for density
As CPP shrinking stalls, chipmakers find a new way to increase transistor density. Imec foresees 0.3nm in 2038, CFET insertion in 2038, HLSI era.
The semiconductor industry is continuously pushing the boundaries of transistor density as current scaling methods face physical limits, necessitating new approaches to maintain performance gains.
This roadmap provides critical insight into the future of semiconductor manufacturing, directly impacting the long-term compute capabilities essential for AI and advanced technology.
The industry's focus is shifting from purely linear shrinkage (CPP) to embracing cell size optimization and novel transistor architectures like CFETs to drive density improvements.
- · ASML
- · TSMC
- · Intel
- · Nvidia
- · Companies reliant on older process nodes
Continued advancement in processor power and efficiency will fuel further innovation in AI and high-performance computing.
The increasing complexity of advanced node development will concentrate manufacturing capabilities among a few highly sophisticated players globally, increasing geopolitical leverage.
The sustained exponential growth in compute power could accelerate the emergence of true general artificial intelligence sooner than widely anticipated.
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Read at Tom's Hardware