Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna)
Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through physical design and... » read more The post Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna) appeared first on Semiconductor Engineering .
The increasing complexity and cost of chip design, coupled with geopolitical pressures on semiconductor supply chains, necessitate accessible and open-source training platforms.
This initiative addresses the critical talent gap in chip design, democratizing access to silicon development and fostering innovation in open-source hardware, which can reduce reliance on proprietary ecosystems.
The availability of an open-source, end-to-end RISC-V platform lowers barriers to entry for chip design education and development, potentially accelerating the adoption of RISC-V and diversifying the talent pool.
- · RISC-V ecosystem
- · Universities and educational institutions
- · Developing nations seeking chip independence
- · Open-source hardware developers
- · Proprietary EDA tool vendors (long-term, marginal)
- · Regions heavily reliant on imported chip design talent
Increased availability of skilled RISC-V chip designers.
Accelerated innovation and adoption of customized RISC-V hardware in various domains.
Emergence of new, localized semiconductor design hubs independent of traditional industry giants.
This signal links to a primary source. Continuum Brief monitors and indexes it as part of the live intelligence stream — we do not republish source content.
Read at Semiconductor Engineering