arXiv:2606.09879v1 Announce Type: new Abstract: This study addresses on-device inference bottlenecks of Transformer models on Tenstorrent's Tensix architecture and proposes an operator fusion strategy that enhances data locality. RMSNorm is fused with matrix multiplication in self-attention and in the FFN, enabling back-to-back execution of memory-bound and compute-bound operators in on-chip SRAM to significantly reduce DRAM reads/writes of intermediate results and scheduling overhead. To support multi-core parallelism, a NoC-based multicast mechanism is leveraged in which row/column master no
The increasing scale of large language models and the demand for efficient on-device inference are driving continuous innovation in hardware-software co-design to mitigate performance bottlenecks.
Optimizing LLM inference on specialized hardware directly impacts the cost, accessibility, and real-world deployment viability of advanced AI, accelerating the adoption of large models in diverse applications.
This research outlines a specific architectural optimization for Tenstorrent's chips that enhances data locality and reduces memory access, potentially improving the competitive positioning of its hardware for LLM workloads.
- · Tenstorrent
- · Developers deploying large language models on edge devices
- · AI hardware architects
- · Competitors with less optimized on-chip memory strategies
- · Systems heavily reliant on high-bandwidth external memory
Improved performance and energy efficiency for LLM inference on Tenstorrent's Tensix architecture.
Increased commercial viability and adoption of Tenstorrent hardware for AI applications requiring on-device LLMs.
Accelerated development and deployment of new AI applications that were previously constrained by inference costs or performance on other architectures.
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Read at arXiv cs.LG