Optimizing ML Workload Partitioning between CPUs and CIM Accelerators for Heterogeneous Computing
arXiv:2607.05240v1 Announce Type: cross Abstract: Computing-in-Memory (CIM) accelerators execute Matrix-Vector Multiplications (MVMs) in memory, making them a compelling solution for Machine Learning (ML) workloads. However, existing ML workload partitioning approaches for CIM accelerators do not fully account for Resistive Random Access Memory (RRAM) constraints such as limited memory, high write latency, and limited endurance. They also neglect parallelism, low-level architectural effects, or the Central Processing Unit (CPU) as a complementary compute resource. To address these limitations,
The increasing demand for AI compute necessitates more efficient hardware architectures and better task distribution strategies to overcome current limitations.
This research optimizes how AI workloads are handled by heterogeneous computing systems, potentially unlocking significant performance improvements and efficiency gains for machine learning at scale.
The proposed methodology better integrates CIM accelerators with traditional CPUs by accounting for practical memory constraints, leading to more effective utilization of advanced hardware.
- · AI hardware developers
- · Cloud computing providers
- · Machine learning researchers
- · Semiconductor manufacturers
- · Inefficient data center operators
- · Traditional CPU-only AI compute
Improved performance and energy efficiency for large-scale AI model training and inference.
Accelerated development and deployment of more complex AI models, particularly in edge computing.
Increased competition among hardware providers to integrate similar optimized partitioning techniques, driving innovation in AI accelerator design.
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Read at arXiv cs.AI