PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
arXiv:2606.15052v1 Announce Type: cross Abstract: Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work, we propose PANDA, an LLM-enhanced framework that bridges high-level design intent to final layout by actively managing cross-stage dependencies through guided topology synthesis, substructure-aware sizing, and constraint-driven layout generation. This shifts automation from algorithm-centric execution to intent-centric co-design, reducing turnaround time from days o
The increasing complexity of advanced silicon and the growing demand for AI accelerators push the limits of traditional analog design, making automation crucial for throughput and efficiency.
This development proposes a significant leap in analog circuit design automation, potentially accelerating the development cycle for critical components in computing infrastructure, especially relevant for AI hardware.
Analog circuit design can shift from heavily manual, isolated stages to an intent-centric, co-design approach managed by AI, significantly reducing design time and effort.
- · Semiconductor companies
- · AI hardware developers
- · EDA tool vendors
- · AI researchers in chip design
- · Manual analog design teams
- · Companies reliant on slow design cycles
Analog circuit design becomes more automated and efficient, leading to faster chip development.
Accelerated chip development could reduce the time-to-market for novel AI hardware and other advanced electronics.
Increased efficiency in analog design might mitigate some aspects of the compute supply chain bottleneck by speeding up component rollout.
This signal links to a primary source. Continuum Brief monitors and indexes it as part of the live intelligence stream — we do not republish source content.
Read at arXiv cs.AI