arXiv:2606.17471v1 Announce Type: new Abstract: Traditional CPU, GPU, and NPU architectures are increasingly limited by the von Neumann bottleneck. While In-Memory Computing (IMC) using ReRAM crossbar arrays offers a high-density, energy-efficient alternative, its practical deployment is constrained through their non-idealities. Existing hardware-aware training frameworks often require training from scratch, which is computationally prohibitive for modern large-scale models. In this work, we propose a finetuning-based hardware-aware training algorithm that enables robust DNN deployment on ReRA
The increasing scale of AI models and the limitations of traditional CPU/GPU architectures are creating an urgent need for more efficient computing paradigms like in-memory computing.
Overcoming the non-idealities of ReRAM in In-Memory Computing is crucial for scaling AI, offering a path to significantly more energy-efficient and dense compute, impacting the foundational costs and capabilities of advanced AI systems.
This finetuning approach makes ReRAM-based in-memory computing more practical for modern large-scale AI models by reducing the computational burden of hardware-aware training.
- · AI developers
- · Semiconductor manufacturers
- · Data center operators
- · ReRAM developers
- · Traditional CPU/GPU architectures (long-term)
- · Companies reliant on current compute efficiency
More energy-efficient and powerful AI hardware accelerates model development and deployment.
Reduced operational costs for AI infrastructure lead to wider adoption and new AI-driven services.
The compute supply chain shifts towards advanced memory and IMC technologies, creating new geopolitical dependencies.
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Read at arXiv cs.LG