Researchers from Université Grenoble Alpes, CNRS, Grenoble INP have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and performance, they also introduce... » read more The post Side-Channel Risks Across Advanced Chiplet Packages (UGA, CNRS) appeared first on Semiconductor Engineering .
The increasing adoption of advanced packaging and chiplet-based integration for complex heterogeneous systems is bringing new security vulnerabilities into focus.
Security risks across advanced chiplet packages could undermine the benefits of modularity and performance, necessitating new design and verification paradigms.
The understanding of chiplet security is evolving, requiring a proactive defense against side-channel attacks in 2.5D/3D integrated systems.
- · Cybersecurity firms specializing in hardware security
- · EDA tool vendors with advanced security verification
- · Chip designers implementing robust security features
- · Academic researchers in hardware security
- · Chip manufacturers without robust security protocols
- · Consumers of insecure advanced chiplet systems
- · Designers relying solely on traditional security measures
Increased investment in hardware-level security for advanced packaging and chiplet designs.
Development of industry standards and best practices for secure 2.5D/3D integration to mitigate side-channel risks.
Potential delays in chiplet adoption or increased manufacturing costs due to the need for stringent security validations.
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