Sign Lock-In: Randomly Initialized Weight Signs Persist and Bottleneck Sub-Bit Model Compression
arXiv:2602.17063v2 Announce Type: replace-cross Abstract: Sub-bit model compression targets storage below one bit per weight; as magnitudes are aggressively compressed, the sign bit becomes a fixed-cost bottleneck. Across Transformers, CNNs, and MLPs, learned sign matrices resist low-rank approximation and are spectrally indistinguishable from an i.i.d. Rademacher baseline. This randomness gives rise to the lower bound of sub-bit model compression -- the one-bit wall. Despite this apparent randomness, most weights retain their initialization signs; flips primarily occur via rare near-zero boun
The paper identifies a fundamental bottleneck in sub-bit model compression, becoming salient as the AI industry rapidly pursues efficiency and deployment on edge devices.
This research provides a theoretical and empirical limit to an important avenue for AI optimization, suggesting that certain compression techniques may hit an 'one-bit wall' due to inherent architectural properties.
The understanding of the fundamental limits of extreme model compression for AI models, redirecting research efforts towards alternative or complementary efficiency methods if sub-bit compression is desired.
- · AI hardware manufacturers specializing in energy efficiency
- · Researchers exploring novel compression techniques beyond weight quantization
- · Developers of specialized AI accelerators that can handle diverse data types
- · Researchers focused solely on aggressive sub-bit weight quantization
- · Developers aiming for ultra-low storage AI models on general-purpose hardware
- · Cloud providers if highly compressed models are not achievable
The sub-bit model compression research direction will face a significant re-evaluation and potential slowdown.
Increased focus will shift to other model efficiency techniques such as sparsity, architecture search, or algorithmic improvements that don't rely heavily on weight quantization.
This could accelerate the development of specialized AI hardware tailored to different forms of model efficiency, rather than just raw computational power or generic low-bit-width processing.
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Read at arXiv cs.CL