Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
arXiv:2606.12983v1 Announce Type: new Abstract: Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate designs must be verified rapidly and reliably. Existing prompt-based approaches treat testbench generation as unconstrained code synthesis, yielding stochastic outputs with high token cost, low reproducibility, and insufficient coverage. To address this gap, we present STG, a Structured Testbench Generation framework that exploits the inherent structure of hardware designs t
The rapid development and integration of LLMs into critical engineering workflows, particularly hardware design, necessitates solutions for their current limitations in 'unconstrained code synthesis'.
This development significantly enhances the reliability and efficiency of LLM-driven hardware design, accelerating time-to-market and reducing verification bottlenecks for complex silicon.
The process of verifying LLM-generated hardware designs becomes more structured and reproducible, moving away from stochastic outputs towards more reliable and coverage-rich testbenches.
- · Semiconductor companies
- · Hardware design engineers
- · AI tool developers
- · Cloud infrastructure providers
- · Traditional manual testbench developers
- · Inefficient LLM code synthesis methods
Faster and cheaper development cycles for new and complex hardware components, especially ASICs for AI.
Increased demand for specialized LLM models trained on hardware description languages and design patterns.
Potential for a significant reduction in hardware development costs, making advanced silicon design more accessible to a broader range of innovators.
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Read at arXiv cs.AI