TSMC says panel packaging won't replace CoWoS anytime soon for the largest future AI processors — wafer-level tech can scale to 58 massive dies in one package
TSMC is exploring panel-level packaging and is working on its CoPoS technology, but the company's Kevin Zhang says wafer-level packaging technologies is considerably more advanced than panel-level packaging.
The rapid increase in demand for advanced AI processors necessitates continuous innovation in packaging technologies to meet performance and integration requirements.
This clarifies the strategic direction of TSMC's advanced packaging efforts, confirming wafer-level CoWoS as the dominant technology for high-end AI chips for the foreseeable future.
The immediate outlook for panel-level packaging as a replacement for CoWoS in large-scale AI processors is diminished, reinforcing CoWoS's critical role in the compute supply chain.
- · TSMC
- · Companies relying on CoWoS for advanced AI chips
- · Ecosystems supporting wafer-level packaging
- · Panel-level packaging startups focused on displacing CoWoS
- · Manufacturers without advanced wafer-level packaging capabilities
Continued reliance on TSMC and its CoWoS technology for the most powerful AI processors.
Increased investment and R&D into further scaling and improving wafer-level packaging to maintain its competitive edge against eventual panel-level solutions.
Potential geopolitical implications as critical AI compute power remains concentrated within the capabilities of a few leading-edge semiconductor manufacturers.
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